中国资本管制 知乎:vhdl语言，帮忙改错！

--TZKZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TZKZQ IS
PORT(
KEY:IN STD_LOGIC_VECTOR(1 DOWNTO 0); --按键信号
CLK_KEY:IN STD_LOGIC; --键盘扫描信号
SEC_EN, MIN_EN, HOUR_EN, WEEK_EN:OUT STD_LOGIC;
--异步并行置位使能
HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
MIN_CUR, SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);
HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);
WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY TZKZQ;
ARCHITECTURE BEHAVE OF TZKZQ IS
TYPE STATETYPE IS(NORMAL,SEC_SET,MIN_SET,HOUR_SET,WEEK_SET);
SIGNAL MODE: STATETYPE;
BEGIN
PROCESS(KEY,CLK_KEY) IS
BEGIN
IF (CLK_KEY'EVENT AND CLK_KEY='1')THEN
IF KEY="01"THEN --如果按下设置键，切换到下一个状态
SEC_EN<='1';MIN_EN<='1';HOUR_EN<='1';WEEK_EN<='1';
CASE MODE IS
WHEN NORMAL=>MODE<=SEC_SET;
SEC<=SEC_CUR;SEC_EN<='0';
--切换到秒设置模式，读入当前秒，秒异步并行置位使能有效
WHEN SEC_SET=>MODE<=MIN_SET;
MIN<=MIN_CUR;SEC_EN<='1';MIN_EN<='0';
--切换到分设置模式，读入当前分，分异步并行置位使能有效，同时秒异步并行置位使能复位
WHEN MIN_SET=>MODE<=HOUR_SET;
HOUR<=HOUR_CUR;MIN_EN<='1';HOUR_EN<='0';
WHEN HOUR_SET=>MODE<=WEEK_SET;
WEEK<=WEEK_CUR;HOUR_EN<='1';WEEK_EN<='0';
WHEN WEEK_SET=>MODE<=NORMAL;
END CASE;
ELSIF KEY="10" THEN --如果按下调试键，则自加
CASE MODE IS
WHEN SEC_SET=>SEC_EN<='0'; --异步并行位使能有效
IF SEC="111011"THEN SEC<="000000";
--如果秒计数到59，返回到0重新计数
ELSE SEC<=SEC+1; --否则继续计数
END IF;
WHEN MIN_SET=>MIN_EN<='0';
IF MIN="111011"THEN MIN<="000000";
ELSE MIN<=MIN+1;
END IF;
WHEN HOUR_SET=>HOUR_EN<='0';
IF HOUR="10111"THEN HOUR<="00000";
ELSE HOUR<=HOUR+1;
END IF;
WHEN WEEK_SET=>WEEK_EN<='0';
IF WEEK="111" THEN WEEK<="001";
ELSE WEEK<=WEEK+1;
END IF;
WHEN OTHERS=>NULL;
END CASE;
END IF;
END IF;
END PROCESS;
END BEHAVE;